Grand Idea Studio

JTAGulator

 

On-chip debug (OCD) interfaces can provide chip-level control of a target device and are a primary vector used by engineers, researchers, and hackers to extract program code or data, modify memory contents, or affect device operation on-the-fly. Depending on the complexity of the target device, manually locating available OCD connections can be a difficult and time consuming task, sometimes requiring physical destruction or modification of the device.

JTAGulator is an open source hardware tool that assists in identifying OCD connections from test points, vias, or component pads on a target device.

Assembled JTAGulators are available from Parallax, Inc. For questions and technical support, please contact support@parallax.com.

This design is distributed under a Creative Commons Attribution-3.0 United States license.

Module Highlights:

  • 24 I/O channels with input protection circuitry
  • Adjustable target voltage for level translation: 1.2V to 3.3V
  • Supported target interfaces: JTAG/IEEE 1149.1, UART/asynchronous serial
  • USB interface for direct connection to host computer

Documentation:

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